Hope I am not out of line here, but last I heard, there is no difference in Address space between ROM and RAM. The only difference in the memory is that you can't write to the ROM (like, it's read-only, duh). There is a write-up about the original ancient architecture of the IBM PC that includes a mention of the infamous 640K barrier on wikipedia here: http://en.wikipedia.org/wiki/IBM_PC "It could take 256 kB of memory on the main board (when 64 Kbit DRAM was introduced); later models were expandable to 640 kB. (The 384 kB of BIOS ROM + video RAM space filled the rest of the one megabyte address space of the 8088 CPU.) It was usually sold with a Monochrome Display Adapter (MDA) video card. " Mileage may vary (well, WILL vary) depending upon the machine (if not PC compatible), however, the principle should remain the same. I could be wrong in my assumptions. It would be possible to have ROM have some sort of special addressing, but why bother? Anyway, (again, last I heard), Intel x86 compatible machines always start the boot sequence in 'REAL' mode. That is, the address space they see is mapped one to one with actual RAM. That means that (in real mode), one can go to absolute 'hardware adresses'. At some point, most operating systems switch the CPU into virtual memory mode. At that point, whatever the software is seeing looks like a big fat (these days) 32/40/48 bit address space. AFAIK, within that space, the ROM is (or at least could be) gone. Regards, Bob Trower > Send Linux mailing list submissions to > linux [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > > To subscribe or unsubscribe via the World Wide Web, visit > http://oclug.on.ca/mailman/listinfo/linux > or, via email, send a message with subject or body 'help' to > linux-request [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > > You can reach the person managing the list at > linux-owner [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of Linux digest..." > > > Today's Topics: > > 1. One last Power on Question. (William Case) > 2. Re: One last Power on Question. (Bart Trojanowski) > 3. Re: [Bulk] Re: [OCLUG-Tech] One last Power on Question. > (William Case) > 4. Re: [Bulk] Re: [OCLUG-Tech] One last Power on Question. > (Bart Trojanowski) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Sat, 08 Sep 2007 09:55:11 -0400 > From: William Case <billlinux [ at ] rogers [ dot ] com> > Subject: [OCLUG-Tech] One last Power on Question. > To: OCLUG Technical <linux [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca> > Message-ID: <1189259711.2697.31.camel@CASE> > Content-Type: text/plain > > Hi; > > This is probably a dumb question to which everybody knows the answer but > me. I have found and received a great deal of valuable help and > explanations regarding what happens between pushing the power button and > a computer begins the actual boot instructions. One question remains > outstanding. > > " ... the CPU starts processing. > > The very first operation performed by a CPU is to fetch an instruction > from address FFFF:0000h. Since this address is almost at the end of > available ROM space, the instruction is almost always a jump command > (JMP) followed by the actual BIOS ROM starting address. ..." > > and further on; > > "... Next, BIOS looks for the presence of a video ROM between memory > locations C000:0000h through C780:000h. In just about all systems, the > search will reveal a video BIOS ROM on a video adapter board plugged > into an available expansion slot. ..." > > In both statements, there is mention of two separate ROM addresses as > opposed to the computer's RAM addresses. How does the CPU know that a > particular address is ROM based, located in a different place than RAM? > For example, using the above mentioned ROM addresses does, the FFFF: or > the C000: signify a specific location for the ROMs? > > I have googled for 'address' and 'memory' and all the variations I can > think of. All answers have explanations of how RAM and VM work -- which > I can follow. None has an explanation of how the CPU finds ROM > addresses. > > Any explanation or guidance would be welcome. > > -- > Regards Bill > > > > ------------------------------ > > Message: 2 > Date: Sat, 8 Sep 2007 10:23:20 -0400 > From: Bart Trojanowski <bart-oclug [ at ] jukie [ dot ] net> > Subject: Re: [OCLUG-Tech] One last Power on Question. > To: William Case <billlinux [ at ] rogers [ dot ] com>, linux [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > Message-ID: <20070908142320 [ dot ] GG20192 [ at ] jukie [ dot ] net> > Content-Type: text/plain; charset=us-ascii > > Bill, > > * William Case <billlinux [ at ] rogers [ dot ] com> [070908 09:54]: > > How does the CPU know that a particular address is ROM based, located > > in a different place than RAM? For example, using the above mentioned > > ROM addresses does, the FFFF: or the C000: signify a specific location > > for the ROMs? > > I am not exactly sure on this, my interest starts after CPU is executing > from RAM. > > However, I know that RAM is not accessible by the (modern) x86 CPU until > it configures the RAM timings. When the CPU is first powered up, code > executes out of instruction cache... how it gets there from ROM I don't > really know. > > I am pretty sure that by the time the main BIOS code searches for the > video BIOS it's already running from a RAM (shadow or copy of ROM). > > You may also want to look at MTRR registers which control how ROM is > shadowed into RAM. > > -Bart > > -- > WebSig: http://www.jukie.net/~bart/sig/ > > > ------------------------------ > > Message: 3 > Date: Sat, 08 Sep 2007 11:27:28 -0400 > From: William Case <billlinux [ at ] rogers [ dot ] com> > Subject: Re: [Bulk] Re: [OCLUG-Tech] One last Power on Question. > To: Bart Trojanowski <bart-oclug [ at ] jukie [ dot ] net> > Cc: linux [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > Message-ID: <1189265248.2697.48.camel@CASE> > Content-Type: text/plain > > Thanks Bart; > On Sat, 2007-09-08 at 10:23 -0400, Bart Trojanowski wrote: > > Bill, > > > However, I know that RAM is not accessible by the (modern) x86 CPU until > > it configures the RAM timings. When the CPU is first powered up, code > > executes out of instruction cache... how it gets there from ROM I don't > > really know. > > > That's the $64,000 question. (Dating myself.) > > > I am pretty sure that by the time the main BIOS code searches for the > > video BIOS it's already running from a RAM (shadow or copy of ROM). > > > > Even if the BIOS is shadowed into RAM, which is what happened on my old > intel P4 and my new AMD 64 Athlon, RAM simply records an address for a > ROM outside of the CPU and RAM. Where does the BIOS get those addresses > and how does the CPU know how to interpret them? Are these addresses > simply a fixed ISA-32 instruction? At the hardware level, a specific > set of gates must be opened that lead to a bus?? that is the pathway to > the ROM? > > > You may also want to look at MTRR registers which control how ROM is > > shadowed into RAM. > > Thanks for the MTRR registers tip. It lead to quite a few information > pages that filled in some of the details I had missed. > > -- > Regards Bill > > > > ------------------------------ > > Message: 4 > Date: Sat, 8 Sep 2007 11:42:44 -0400 > From: Bart Trojanowski <bart-oclug [ at ] jukie [ dot ] net> > Subject: Re: [Bulk] Re: [OCLUG-Tech] One last Power on Question. > To: William Case <billlinux [ at ] rogers [ dot ] com>, linux [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > Message-ID: <20070908154244 [ dot ] GI20192 [ at ] jukie [ dot ] net> > Content-Type: text/plain; charset=us-ascii > > * William Case <billlinux [ at ] rogers [ dot ] com> [070908 11:27]: > > That's the $64,000 question. (Dating myself.) > > Don't you mean $65,536 question? > > > Even if the BIOS is shadowed into RAM, which is what happened on my old > > intel P4 and my new AMD 64 Athlon, RAM simply records an address for a > > ROM outside of the CPU and RAM. Where does the BIOS get those addresses > > and how does the CPU know how to interpret them? Are these addresses > > simply a fixed ISA-32 instruction? At the hardware level, a specific > > set of gates must be opened that lead to a bus?? that is the pathway to > > the ROM? > > If you are asking about the "rest" of the BIOS, I think this is an > implementation specific detail. It could be stored at some higher 32bit > page, it could be fetched using something similar to the CMOS register > access. > > You can have a look at... > > http://www.jukie.net/~bart/blog/bios-disassembler > > This let me follow the BIOS code from a machine I was doing some low > level hacking on. > > -Bart > > -- > WebSig: http://www.jukie.net/~bart/sig/ > > > ------------------------------ > > _______________________________________________ > Linux mailing list > Linux [ at ] lists [ dot ] oclug [ dot ] on [ dot ] ca > http://oclug.on.ca/mailman/listinfo/linux > > > End of Linux Digest, Vol 33, Issue 3 > ************************************ > >