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Re: [Bulk] Re: [OCLUG-Tech] One last Power on Question.

Thanks Bart;
On Sat, 2007-09-08 at 10:23 -0400, Bart Trojanowski wrote:
> Bill,

> However, I know that RAM is not accessible by the (modern) x86 CPU until
> it configures the RAM timings.  When the CPU is first powered up, code
> executes out of instruction cache... how it gets there from ROM I don't
> really know.
> 
That's the $64,000 question.  (Dating myself.)

> I am pretty sure that by the time the main BIOS code searches for the
> video BIOS it's already running from a RAM (shadow or copy of ROM).
> 

Even if the BIOS is shadowed into RAM, which is what happened on my old
intel P4 and my new AMD 64 Athlon, RAM simply records an address for a
ROM outside of the CPU and RAM.  Where does the BIOS get those addresses
and how does the CPU know how to interpret them?  Are these addresses
simply a fixed ISA-32 instruction?  At the hardware level, a specific
set of gates must be opened that lead to a bus?? that is the pathway to
the ROM?

> You may also want to look at MTRR registers which control how ROM is
> shadowed into RAM.

Thanks for the MTRR registers tip.  It lead to quite a few information
pages that filled in some of the details I had missed.

-- 
Regards Bill